View THC63LVDM83D-16_8739981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

continuing its rich tradition of partnering with high quality japanese semiconductor suppliers, cel is now partnering with thine from may of 2015 onwards. to our customers www.cel.com
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 1/17 thine electronics, inc. security e 7 pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz data (lvds) (56-1120mbit/on each lvds channel) clkin thc63lvdm83d 7 pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz data (lvds) (56-1120mbit/on each lvds channel) clkin thc63lvdm83d thc63lvdm83d 24bit color lvds transmitter general description the thc63lvdm83d transmitter is designed to support pixel data transmission between host and flat panel display up to 1080p/wuxga resolutions. the thc63lvdm83d converts 28bits of lvcmos data into four lvds data streams. the transmitter can be programmed for rising edge or falling edge clock through a dedicated pin. at a transmit clock frequency of 160mhz, 24bits of rgb data and 4bits of timing and control data (hsync, vsync, de, cont1) are transmitted at an effective rate of 1120mbps per lvds channel. application medium and small size panel tablet pc / notebook pc security camera / industrial camera multi function printer industrial equipment medical equipment monitor features compatible with tia/eia-644 lvds standard 7:1 lvds transmitter operating temperature range : 0 to +70 c no special start-up sequence required spread spectrum clocking tolerant up to 100khz frequency modulation and +/-2.5% deviations. wide dot clock range: 8 to 160mhz suited for tv signal : ntsc(12.27mhz) - 1080p(148.5mhz) pc signal : qvga(8mhz) - wuxga(154mhz) 56pin tssop package 1.2v to 3.3v lvcmos/ inputs are supported. lvdsswingisreducibleas200mvbyrs-pintoreduceemi and power consumption. pll requires no external components. power down mode. input clock triggering edge is selectable by r/f-pin eu rohs compliant. block diagram figure 1. block diagram
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 2/17 thine electronics, inc. security e pin diagram figure 2. pin diagram
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 3/17 thine electronics, inc. security e pin description pin nam e pin # direction typ e description ta+, ta- 47, 48 output lvds lvds data out tb+, tb- 45, 46 tc+, tc- 41, 42 td+, td- 37, 38 tclk+, tclk- 39, 40 lvds clock out ta0 ~ ta6 51, 52, 54, 55, 56, 3, 4 input lvcmos pixel data input tb0 ~ tb6 6, 7, 11, 12, 14, 15, 19 tc0 ~ tc6 20, 22, 23, 24, 27, 28, 30 td0 ~ td6 50, 2, 8, 10, 16, 18, 25 /pdwn 32 h : normal operation l : power down (all outputs are hi-z) rs 1 lvds swing mode, vref select see fig.8, 9 vref : is input reference voltage r/f 17 input clock triggering edge select h:risingedge l : falling edge clkin 31 input clock vcc 9, 26 power - power supply pins for lvcmos inputs and digital circuit. gnd 5, 13, 21, 29, 53 ground pins for lvcmos inputs and digital circuitry. lvds vcc 44 power supply pins for lvds outputs. lvds gnd 36, 43 49 ground pins for lvds outputs. pll vcc 34 power supply pin for pll circuitry. pll gnd 33, 35 ground supply pin for pll circuitry. table 1. pin description rs lvds swing small swing input support vcc 350mv n/a 0.6 ~ 1.4v 350mv rs=vref gnd 200mv n/a
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 4/17 thine electronics, inc. security e absolute maximum ratings parameter min max unit supply voltage (vcc) -0.3 +4.0 v lvcmos input voltage -0.3 vcc + 0.3 v lvds output pin -0.3 vcc + 0.3 v output current -30 30 ma junction temperature -+125 c storage temperature -55 +150 c reflow peak temperature -+260 c reflow peak temperature time - 10 sec maximum power dissipation @+25 c -1.8w table 2. absolute maximum ratings recommended operating conditions symbol parameter min typ max unit - all supply voltage 3.0 3.3 3.6 v ta operating ambient temperature 0 25 +70 c - clock frequency 8 - 160 mhz table 3. recommended operating conditions ?absolute maximum ratings? are those values beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of ?electrical characteristics table4, 5, 6, 7? specify conditions for device operation. ?absolute maximum rating? value also includes behavior of overshooting and undershooting. equivalent lvds output schematic diagram figure 3. lvds output schematic diagram
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 5/17 thine electronics, inc. security e clkin tx0-6 power consumption over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions typ* max unit i tccw lvds transmitter operating current worst case pattern (fig.4) rl=100 , cl=5pf, f=85mhz, rs=vcc 61 67 ma rl=100 , cl=5pf, f=135mhz, rs=vcc 77 83 ma rl=100 , cl=5pf, f=160mhz, rs=vcc 84 92 ma rl=100 , cl=5pf, f=85mhz, rs=gnd 50 56 ma rl=100 , cl=5pf, f=135mhz, rs=gnd 65 71 ma rl=100 , cl=5pf, f=160mhz, rs=gnd 73 80 ma i tccs lvds transmitter power down current /pdwn=l, all inputs=l or h - 10 a *typ values are at the conditions of vcc=3.3v and ta = +25oc table 4. power consumption worst case pattern x=a,b,c,d figure 4. worst case pattern
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 6/17 thine electronics, inc. security e electrical characteristics lvcmos dc specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions min typ* max unit v i h high level input voltage rs=vcc or gnd 2.0 - vcc v v il low level input voltage rs=vcc or gnd gnd - 0.8 v v dd q 1 small swing voltage 1.2 - 2.8 v v re f input reference voltage small swing (rs=v dd q /2) - v dd q /2 - v sh 2 small swing high level input voltage v ref= v ddq /2 v ddq /2 +100m v --v v sl 2 small swing low level input voltage v ref= v ddq /2 - - v ddq /2 -100mv v i inc input current gnd v i n vcc -- 10 a *typ values are at the conditions of vcc=3.3v and ta = +25oc notes : 1 v ddq voltage defines the max voltage of small swing inputs at rs=vref. it is not an actual input voltage. 2 small swing signals are applied to ta0-6, tb0-6, tc0-6, td0-6 and clkin. table 5. lv-cmos dc specifications lvds transmitter dc specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions min typ* max unit vod differential output voltage normal swing rs=vcc 250 350 450 mv reduced swing rs=gnd 100 200 300 mv complementary output states --35mv voc common mode voltage 1.125 1.25 1.375 v complementary output states --35mv i os output short circuit current v out ---24ma i oz output tri-state current /pdwn=gnd, v out =gnd to vcc -- 10 a *typ values are at the conditions of vcc=3.3v and ta = +25oc table 6. lvds transmitter dc specifications
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 7/17 thine electronics, inc. security e clk in 90% 10% 90% 10% t tcit t tcit lvcmos & lvds transmitter ac specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter min typ max unit t tcit clk in transition time - - 5.0 ns t tc p clk in period 6.25 t 125 ns t tc h clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/- delay - 3t - ns t t s lvcmosdatasetuptoclkin 2.0 - - ns t t h lvcmos data hold from clk in 0.0 - - ns t lvt lvds transition time - 0.6 1.5 ns t top1 output data position0 (t=6.25ns ~ 20ns) -0.15 0.0 +0.15 ns t to p 0 output data position1 (t=6.25ns ~ 20ns) t/7-0.15 t/7 t/7+0.15 ns t to p6 output data position2 (t=6.25ns ~ 20ns) 2t/7-0.15 2t/7 2t/7+0.15 ns t to p5 output data position3 (t=6.25ns ~ 20ns) 3t/7-0.15 3t/7 3t/7+0.15 ns t to p 4 output data position4 (t=6.25ns ~ 20ns) 4t/7-0.15 4t/7 4t/7+0.15 ns t to p3 output data position5 (t=6.25ns ~ 20ns) 5t/7-0.15 5t/7 5t/7+0.15 ns t to p2 output data position6 (t=6.25ns ~ 20ns) 6t/7-0.15 6t/7 6t/7+0.15 ns t tpll phase lock loop set - - 10.0 ms *typ values are at the conditions of vcc=3.3v and ta = +25oc table 7. lvcmos & lvds transmitter ac specifications lvcmos input figure 5. clkin transmission time lvds output lvds output load figure 6. lvds output load and transmission time
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 8/17 thine electronics, inc. security e rs vod vcc 0.6 ~ 1.4v gnd 200mv 350mv rs vref vcc --- 0.6 ~ 1.4v v ddq /2 gnd --- ttcp tts tth ttch ttcl clkin tx0-tx6 ttcd tclk+ tclk- v ddq gnd gnd v ddq voc ttcp tts tth ttch ttcl clkin tx0-tx6 ttcd tclk+ tclk- v ddq gnd gnd v ddq v ref voc v ref v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ddq /2 ac timing diagrams lv c m o s i n p u t s note : clkin : solis line denotes the setting of r/f=gnd dashed line denotes the setting of r/f = vcc figure 7. lvcoms inputs and lvds clock output timing 1 small swing inputs note : clkin : solid line denotes the setting of r/f=gnd dashed line denotes the setting of r/f = vcc figure 8. lvcmos inputs and lvds output timing 2
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 9/17 thine electronics, inc. security e v diff =0v v diff =0v tclk+/- t top1 t to p0 t to p6 t to p5 t to p4 t to p3 t to p2 td6 td5 td4 td 3 td2 td1 td0 td+/- tc6 tc5 tc4 tc 3 tc2 tc1 tc0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) nex t cy cle previous cycle 2.0v clkin /pdwn tclk+/- 3.0v vcc t tpll v di ff =0v lvds output data position figure 9. lvds output data position phase lock loop set time figure 10. pll lock loop set time
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 10/17 thine electronics, inc. security e spread spectrum clocking tolerant figure 11. spread spectrum clocking tolerant the graph indicates the range that the ic works normally under ss clock input operation. the results are measured with a typical sample on condition of +25co and 3.3v, therefore these values are for reference and do not guarantee the performance of a product under other circumstance.
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 11/17 thine electronics, inc. security e lvds data timing diagram figure 12. lvds data timing diagram thc63lvdm83d pixel data mapping for jeida format (6bit, 8bit application) note : use ta to tc channels and open td channel for 6bit application. table 8. data mapping for jeida format 6bit 8bit ta 0 r2 r2 ta 1 r3 r3 ta 2 r4 r4 ta 3 r5 r5 ta 4 r6 r6 ta 5 r7 r7 ta 6 g2 g2 tb0 g3 g3 tb1 g4 g4 tb2 g5 g5 tb3 g6 g6 tb4 g7 g7 tb5 b2 b2 tb6 b3 b3 tc0 b4 b4 tc1 b5 b5 tc2 b6 b6 tc3 b7 b7 tc4 hsync hsync tc5 vsync vsync tc6 de de td0 - r0 td1 - r1 td2 - g0 td3 - g1 td4 - b0 td5 - b1 td6 - n/a
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 12/17 thine electronics, inc. security e thc63lvdm83d pixel data mapping for vesa format (6bit, 8bit application) note : use ta to tc channels and open td channel for 6bit application. table 9. data mapping for vesa format 6bit 8bit ta 0 r0 r0 ta 1 r1 r1 ta 2 r2 r2 ta 3 r3 r3 ta 4 r4 r4 ta 5 r5 r5 ta 6 g0 g0 tb0 g1 g1 tb1 g2 g2 tb2 g3 g3 tb3 g4 g4 tb4 g5 g5 tb5 b0 b0 tb6 b1 b1 tc0 b2 b2 tc1 b3 b3 tc2 b4 b4 tc3 b5 b5 tc4 hsync hsync tc5 vsync vsync tc6 de de td0 - r6 td1 - r7 td2 - g6 td3 - g7 td4 - b6 td5 - b7 td6 - n/a
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 13/17 thine electronics, inc. security e normal connection figure 13. typical connection diagram
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 14/17 thine electronics, inc. security e notes 1) cable connection and disconnection do not connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection connect each gnd of the pcb which thc63lvdm83d and lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3) multi drop connection multi drop connection is not recommended. figure 14. multi drop connection 4) asynchronous use asynchronous using such as following systems is not recommended. figure 15. asynchronous use lvds-rx thc63lvdm83d lvds-rx tclk+ tclk- ic clkout clkout data dat a lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data th c 63lvdm83d thc63lvdm83d ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic thc63lvdm83d thc63lvdm83d
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 15/17 thine electronics, inc. security e package figure 16. package diagram
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 16/17 thine electronics, inc. security e reference land pattern figure 17. reference of land pattern the recommendation mounting method of thine device is reflow soldering. the reference pattern is using the calculation result on condition of reflow soldering. notes this land pattern design is a calculated value based on jeita et-7501. please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connection, the density of mounting, and the solder paste used, etc? the optimal land pattern size changes with these parameters. please use the value shown by the land pattern as reference data.
thc63lvdm83d_rev.4.20_e copyright?2015 thine electronics, inc. 17/17 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (?thine?) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product. except where mandated by applicable law or deemed necessary by thine based on the user?s request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damages may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp

▲Up To Search▲

Price & Availability of THC63LVDM83D-16

	To Download THC63LVDM83D-16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .